As a matter of course, the utilization scope of an LSI in a computer has been enlarged for communicating apparatuses such as a portable telephone, general household appliances, toys and cars. On the other hand, however, there are problems in that an electromagnetic interference (EMI) generated from these products causes the radio interference of a receiver such as a television or a radio and the malfunction of other systems. A countermeasure in the whole products such as filtering or shielding has also been taken against these problems. In respect of an increase in the number of components, an increase in a cost and the difficulty of a countermeasure in a product, the noise suppression of an LSI package has been greatly demanded.
In such a situation, the LSI of each product is placed as a key device and an increase in the scale and speed of the LSI has been demanded in order to maintain the competitiveness of the product. In order to meet these demands in a reduction in a product cycle, it is necessary to automate an LSI design. There has been increased a necessity for employing a synchronous design as the condition of the introduction of a design automation technique under the existing circumstances. If all circuits are operated synchronously with a reference clock and the LSI has a large scale and a high speed, an instantaneous current is very increased. Consequently, an increase in the electromagnetic interference is caused.
With the microfabrication of the LSI and an increase in the speed of an operating frequency, thus, countermeasures against latch up and a noise have been great problems.
In a method of designing a cell base, generally, a diffusion region and a through hole are formed in a substrate cell as the countermeasure against latch up. Consequently, a contact is formed and a substrate or a well is fixed to have a supply potential through the contact.
If a substrate contact is added into the substrate cell as the countermeasure against latch up, however, a chip area is increased.
The inventors have proposed a method of enhancing a latch up breakdown voltage, reducing a noise radiation and reducing a malfunction caused by a noise entering from the outside while suppressing an increase in the area of a semiconductor device by providing a substrate contact under a power wiring and arranging a capacitor having a cell bypassed between the power wiring and a ground wiring in order to prevent an increase in a chip area (JP-A-2000-208634).
The method serves to automatically generate the pattern of a semiconductor device, comprising the steps of generating a layout including a cell having an MIS structure on a semiconductor substrate and the pattern of a power wiring and a ground wiring, generating a layout including a cell having an MIS structure on the semiconductor substrate and the patterns of a power wiring and a ground wiring, and automatically generating the pattern of a bypass capacitor having the MIS structure constituted by the semiconductor substrate, a capacitive insulating film and an electrode to overlap with the pattern of the power wiring.
According to this method, the power wiring pattern has already been formed before the formation of the bypass capacitor including a diffusion layer and a through hole. Therefore, the bypass capacitor can be formed by utilizing the power wiring pattern so that a high integrated semiconductor device can easily be formed.
As a specific example, FIG. 20 shows an example of the bypass capacitor, in which the bypass capacitor is formed between a polysilicon electrode (gate electrode) 71 and a substrate, and a capacitive insulating film (a gate insulating film which is not shown) provided therebetween, and a diffusion region is formed to take the shape of a ring in a region corresponding to the outer periphery of a gate electrode, a virtual power wiring pattern in a transverse direction and a virtual power wiring pattern in a vertical direction are extracted in place of an original power wiring pattern by using a kind of bypass capacitor array in which an electric potential on the substrate side is fetched and connected in the diffusion region, and a bypass capacitor frame 70 including them is formed. Moreover, a through hole 72 is formed on the surface of the polysilicon electrode 71 in order to fetch an electric potential on the polysilicon electrode side. Consequently, the pattern of a semiconductor device provided with a bypass capacitor having the ring-shaped polysilicon electrode 71 under a power wiring is generated.
According to this method, it is possible to reduce a power noise which becomes more serious with the microfabrication of a semiconductor device and an increase in the speed of an operating frequency. However, the effect of reducing the power noise cannot be fully produced. Moreover, portions in which a decoupling capacity is to be inserted are decreased with an increase in the integration of the semiconductor device. Thus, there is a problem in that a sufficient decoupling capacity cannot be obtained.
Furthermore, it is necessary to take a pattern direction and a wiring direction into consideration in the addition of a capacity. In a conventional pattern generating method, consequently, automation is hard to perform.
Therefore, it has been demanded that a bypass capacitor having a larger capacity is formed without an increase in an occupied area in order to reduce a power noise more reliably.
In the method, moreover, the operating frequency is not taken into consideration. In a semiconductor device to be driven at a specific operating frequency, the effect of reducing a power noise cannot be sufficiently obtained.
Thus, the use of the bypass capacitor comprising polysilicon constituting a gate electrode, a bypass capacitor diffusion provided to take the shape of a ring on the outside of the polysilicon, and a bypass capacitor contact provided on the polysilicon cannot take a countermeasure for absorbing a power noise for each frequency characteristic.
Although a capacitor having a large capacity may be provided in an ESD and a wiring between blocks and a capacitor having a small capacity may be provided between the blocks in the same chip, moreover, the same noise countermeasure is entirely taken and is not always effective.
The invention has been made in consideration of the actual circumstances and has an object to effectively absorb a power noise and to implement the stable operation of a circuit.
It is another object of the invention to easily automate pattern generation in order to reliably reduce a power noise.
It is yet another object of the invention to form a capacitor having a larger capacity without increasing an occupied area in order to reduce a power noise more reliably.
It is a further object of the invention to implement the stable operation of a circuit by properly using a capacity to absorb a power noise depending on an operating frequency characteristic.